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®
Altera Corporation 1
MAX 9000
Programmable Logic
Device Family
June 2003, ver. 6.5 Data Sheet
DS-M9000-6.5
Includes
MAX 9000A
Features...
High-performance CMOS EEPROM-based programmable logic
devices (PLDs) built on third-generation Multiple Array MatriX
(MAX
®
) architecture
5.0-V in-system programmability (ISP) through built-in IEEE Std.
1149.1 Joint Test Action Group (JTAG) interface
Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE
Std. 1149.1-1990
High-density erasable programmable logic device (EPLD) family
ranging from 6,000 to 12,000 usable gates (see Table 1)
10-ns pin-to-pin logic delays with counter frequencies of up to
144 MHz
Fully compliant with the peripheral component interconnect Special
Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2
Dual-output macrocell for independent use of combinatorial and
registered logic
FastTrack
®
Interconnect for fast, predictable interconnect delays
Input/output registers with clear and clock enable on all I/O pins
Programmable output slew-rate control to reduce switching noise
MultiVolt
I/O interface operation, allowing devices to interface with
3.3-V and 5.0-V devices
Configurable expander product-term distribution allowing up to 32
product terms per macrocell
Programmable power-saving mode for more than 50% power
reduction in each macrocell
Table 1. MAX 9000 Device Features
Feature EPM9320
EPM9320A
EPM9400 EPM9480 EPM9560
EPM9560A
Usable gates 6,000 8,000 10,000 12,000
Flipflops 484 580 676 772
Macrocells 320 400 480 560
Logic array blocks (LABs) 20 25 30 35
Maximum user I/O pins 168 159 175 216
t
PD1
(ns) 10 15 10 10
t
FSU
(ns) 3.0 5 3.0 3.0
t
FCO
(ns) 4.5 7 4.8 4.8
f
CNT
(MHz) 144 118 144 144
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Shrnutí obsahu

Strany 1 - MAX 9000

®Altera Corporation 1MAX 9000Programmable LogicDevice FamilyJune 2003, ver. 6.5 Data SheetDS-M9000-6.5IncludesMAX 9000AFeatures... High-performance

Strany 2 - Features

10 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetExpander Product TermsAlthough most logic functions can be implemented with t

Strany 3 - Description

Altera Corporation 11MAX 9000 Programmable Logic Device Family Data SheetParallel ExpandersParallel expanders are unused product terms that can be al

Strany 4 - 4 Altera Corporation

12 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetThe MAX+PLUS II Compiler automatically allocates as many as three sets of up

Strany 5 - Functional

Altera Corporation 13MAX 9000 Programmable Logic Device Family Data SheetFigure 6. MAX 9000 Device Interconnect ResourcesThe LABs within MAX 9000 dev

Strany 6 - Logic Array Blocks

14 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetEach row of LABs has a dedicated row interconnect that routes signals both in

Strany 7

Altera Corporation 15MAX 9000 Programmable Logic Device Family Data SheetA row interconnect channel can be fed by the output of the macrocell through

Strany 8 - Macrocells

16 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetFigure 9. MAX 9000 Column-to-IOC ConnectionsDedicated InputsIn addition to th

Strany 9 - Altera Corporation 9

Altera Corporation 17MAX 9000 Programmable Logic Device Family Data SheetFigure 10. MAX 9000 IOCI/O pins can be used as input, output, or bidirection

Strany 10 - Expander Product Terms

18 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetThe output buffer in each IOC has an adjustable output slew rate that can be

Strany 11 - Parallel Expanders

Altera Corporation 19MAX 9000 Programmable Logic Device Family Data SheetThe VCCIO pins can be connected to either a 3.3-V or 5.0-V power supply, dep

Strany 12 - FastTrack Interconnect

2 Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet...and More Features Programmable macrocell flipflops with individual clear,

Strany 13

20 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetProgramming SequenceDuring in-system programming, instructions, addresses, an

Strany 14 - Local Array

Altera Corporation 21MAX 9000 Programmable Logic Device Family Data SheetBy combining the pulse and shift times for each of the programming stages, t

Strany 15 - Row-to-I/O Cell Connections

22 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetThe programming times described in Tables 7 through 9 are associated with the

Strany 16 - Dedicated Inputs

Altera Corporation 23MAX 9000 Programmable Logic Device Family Data SheetProgramming with External HardwareMAX 9000 devices can be programmed on Wind

Strany 17

24 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetThe instruction register length for MAX 9000 devices is 10 bits. EPM9320A and

Strany 18 - Configuration

Altera Corporation 25MAX 9000 Programmable Logic Device Family Data SheetFigure 11. MAX 9000 JTAG WaveformsTable13 shows the JTAG timing parameters a

Strany 19 - Programma

26 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetProgrammable Speed/Power ControlMAX 9000 devices offer a power-saving mode th

Strany 20 - Programming Times

Altera Corporation 27MAX 9000 Programmable Logic Device Family Data SheetOperating ConditionsTables 14 through 20 provide information on absolute max

Strany 21

28 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetTable 16. MAX 9000 Device DC Operating Conditions Notes (5), (6)Symbol Parame

Strany 22

Altera Corporation 29MAX 9000 Programmable Logic Device Family Data SheetNotes to tables:(1) See the Operating Requirements for Altera Devices Data S

Strany 23

Altera Corporation 3MAX 9000 Programmable Logic Device Family Data SheetGeneral DescriptionThe MAX 9000 family of in-system-programmable, high-densit

Strany 24

30 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetTiming ModelThe continuous, high-performance FastTrack Interconnect ensures p

Strany 25

Altera Corporation 31MAX 9000 Programmable Logic Device Family Data SheetFigure 14. MAX 9000 Timing ModelMacrocelltRDtCOMBtSUtHtPREtCLRMacrocell/Regi

Strany 26 - Generic Testing

32 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetTables 21 through 24 show timing for MAX 9000 devices.Table 21. MAX 9000 Exte

Strany 27 - Conditions

Altera Corporation 33MAX 9000 Programmable Logic Device Family Data SheetTable 22. MAX 9000 Internal Timing Characteristics Note (1)Symbol Parameter

Strany 28

34 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetTable 23. IOC DelaysSymbol Parameter Conditions Speed Grade Unit-10 -15 -20Mi

Strany 29

Altera Corporation 35MAX 9000 Programmable Logic Device Family Data SheetNotes to tables:(1) These values are specified under the MAX 9000 device rec

Strany 30 - Timing Model

36 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetThe parameters in this equation are shown below:MCTON= Number of macrocells

Strany 31 - Macrocell

Altera Corporation 37MAX 9000 Programmable Logic Device Family Data SheetFigure 15. ICC vs. Frequency for MAX 9000 Devices (Part 1 of 2)0Frequency (M

Strany 32 - Min Max Min Max Min Max

38 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetFigure 15. ICC vs. Frequency for MAX 9000 Devices (Part 2 of 2)Device Pin-Out

Strany 33

Altera Corporation 39MAX 9000 Programmable Logic Device Family Data SheetGND 6, 18, 24, 25, 48, 61, 67, 7014, 20, 24, 31, 35, 41, 42, 43, 44, 46, 47,

Strany 34 - MinMaxMinMaxMinMax

4 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetAll MAX 9000 device packages provide four dedicated inputs for global control

Strany 35 - Consumption

40 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetNotes:(1) All pins not listed are user I/O pins.(2) Perform a complete therma

Strany 36

Altera Corporation 41MAX 9000 Programmable Logic Device Family Data SheetNotes:(1) All pins not listed are user I/O pins.(2) During in-system program

Strany 37 - Figure 15. I

42 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetTable 29. EPM9560 & EPM9560A Dedicated Pin-Outs (Part 1 of 2) Note (1)Pi

Strany 38 - Pin-Outs

Altera Corporation 43MAX 9000 Programmable Logic Device Family Data SheetNotes:(1) All pins not listed are user I/O pins.(2) EPM9560A devices are not

Strany 39

Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, thestylized Altera logo, specific device designa

Strany 40

Altera Corporation 45MAX 9000 Programmable Logic Device Family Data Sheet

Strany 41 - VPP pin is pulled up

46 Altera CorporationMAX 9000 Programmable Logic Device Family Data Sheet

Strany 42

Altera Corporation 5MAX 9000 Programmable Logic Device Family Data SheetThe MAX 9000 family is supported by Altera’s MAX+PLUS II development system,

Strany 43

6 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetFigure 1. MAX 9000 Device Block DiagramLogic Array BlocksThe MAX 9000 architec

Strany 44 - Revision

Altera Corporation 7MAX 9000 Programmable Logic Device Family Data SheetLABs drive the row and column interconnect directly. Each macrocell can drive

Strany 45 - Altera Corporation 45

8 Altera CorporationMAX 9000 Programmable Logic Device Family Data SheetMacrocellsThe MAX 9000 macrocell consists of three functional blocks: the prod

Strany 46 - 46 Altera Corporation

Altera Corporation 9MAX 9000 Programmable Logic Device Family Data SheetFor registered functions, each macrocell register can be individually program

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